Reconfiguring SGM61630 Series Buck Converter as an Inverting Buck-Boost Converter

Author: Kai Deng
Corresponding Author: Cherry Cheng
Reviewers: Hui Liu, Jason Liu

ABSTRACT

This document takes the SGM61630 as an example to systematically present the design methodology for reconfiguring a Buck converter into an inverting Buck-Boost converter to generate a stable negative power rail. The design procedure is elaborated through topology connection adjustment, voltage and current stress analysis, and auxiliary function design. Finally, a design example verifies the feasibility of achieving a 15 V/1.5 A output from a 24 V input. This document provides engineers with a complete design workflow from theoretical derivation to practical validation.

1 Introduction

Many precision systems (such as medical electronic equipment and test and measurement instruments) require a stable negative voltage supply while also requiring the input and output to share a common ground. An inverting Buck-Boost converter perfectly meets this requirement, as it not only achieves step-up/step down functionality but also inverts the output voltage polarity. By adjusting the power stage topology connection and feedback network parameters, any conventional Buck converter can be reconfigured as an inverting Buck-Boost converter. This document takes the SGM61630 as an example to elaborate on its reconfiguration method and design considerations. This approach is applicable to the implementation of inverting Buck-Boost converters in both synchronous rectification and non-synchronous rectification architectures.

2 Inverting Buck-Boost Converter Principle

2.1 Topology Reconfiguration and Connection Method

Figure 1 shows the basic topology of a Buck converter. In the Buck configuration, the output positive terminal (V_OUT) is connected to the inductor, while the output negative terminal is connected to the GND pin of the Buck IC.

The inverting Buck-Boost topology is very similar to the Buck topology. Figure 2 shows the connection method for reconfiguring a Buck converter as an inverting Buck-Boost converter. As shown in Figure 2, the positive output terminal of the Buck converter is configured as the system ground (System GND) of the inverting Buck-Boost converter, while "IC GND" becomes the negative output terminal (-V_OUT). An additional input capacitor C_IN is added between the input power supply and the system ground. It should be noted that in the connection method of the inverting Buck-Boost converter, IC GND is directly connected to the negative output voltage, which affects the voltage stress on the pins of the Buck IC. The external circuits for the relevant control pins must be redesigned, as detailed in the "3 Auxiliary Function" section.

After the above steps, the reconfiguration of the inverting Buck-Boost converter is achieved: when the MOSFET is turned on, the power diode is reverse-biased, the voltage across the inductor is V_IN, the inductor current rises, and the output capacitor C_OUT supplies energy to the load, as shown in Figure 3 (a); when the MOSFET is turned off, the power diode conducts, the voltage across the inductor is -V_OUT, the inductor current decreases, and the inductor current supplies energy to the load, as shown in Figure 3 (b). The duty cycle D in continuous conduction mode (CCM) is given by:

2.2 Voltage and Current Stress Analysis

Configuring a Buck IC as an inverting Buck-Boost converter requires special attention to voltage requirements. From Figure 2, it can be seen that the voltage difference between the VIN and GND pins of the Buck IC equals the input voltage plus the output voltage (V_MAX=V_IN+V_OUT) of the power module. For example, for a conversion from a +24 V input to a -15 V output, a Buck IC with an input voltage range covering at least 39 V is required. When the MOSFET is turned on, the voltage stress across the power diode is also the input voltage plus the output voltage (V_MAX=V_IN+V_OUT), which should be considered when selecting the power diode.

As shown in Figure 2, the capacitor C_IO connected between V_IN and -V_OUT also withstands a voltage stress of (V_IN+V_OUT). However, it is worth noting that if V_IN is powered up quickly, a transient current is generated at the moment of power-up. Its path is: V_IN → C_IO → IC GND → power diode → inductor → System GND. This transient current may have the following effects on the circuit: (1) When the transient current flows through the power diode (or the body diode of a synchronous Buck IC), the SW node potential may be pulled below IC GND. For devices with a small rated voltage of SW relative to IC GND, such negative voltage transients may damage the device; (2) The transient current flowing through the power inductor generates an induced electromotive force. The combined effect of the diode and the induced electromotive force results in a transient positive voltage on V_OUT. Therefore, based on the trade-off between protecting against the transient voltages mentioned above and decoupling the Buck IC VIN pin, it is recommended that the C_IO capacitor not be too large; a value of 0.1 μF is generally recommended.

In the Buck converter configuration, the inductor always supplies current to the load during both the MOSFET on-time and off-time, so the average inductor current of the Buck converter equals the output current. However, in the inverting Buck-Boost converter configuration, the energy in the inductor is delivered to the load only during the MOSFET off-time via the diode. The inductor current calculation formulas for the two topologies are shown in Table 1.

As can be seen from Table 1, under the same load, the inductor peak current of the inverting Buck-Boost converter is larger. During reconfiguration, care must be taken to ensure that the inductor peak current does not exceed the peak current limit specified in the Buck IC datasheet.

For specific calculations using the SGM61630 as an example, please refer to the "4 Design Example" section.

3 Auxiliary Function

In the inverting Buck-Boost converter configuration, IC GND is directly connected to the negative output voltage. Since all control signal levels of the Buck IC are referenced to IC GND, if these functions need to be used in the system, the reference level of the control signals must be shifted to the system ground.

3.1 Enable Signal Interface Design

If the system is not required to control enable signal, the EN pin can be pulled up to V_IN through a resistor. If the system is required to control the enable function of the inverting Buck-Boost converter, a simple level shifting circuit is needed, as shown in Figure 4.

When SYS_EN provides a sufficiently high positive voltage to turn on Q1, the gate of Q2 is connected to ground through Q1, making the gate-source voltage (V_GS) of Q2 negative, thereby turning on Q2. At this time, the input voltage (V_IN) is connected to the EN pin through the resistor divider, enabling the device. It should be noted that in both the enable and disable states, the gate-drain voltage (V_GD) and gate-source voltage (V_GS) of Q2 must remain within the MOSFET's rated range. Taking the SGM61630 as an example, set R_EN1 = R_EN2 = R1 = 100kΩ in Figure 4. Figure 5 shows the waveforms for system-controlled enabling and disabling of the inverting buck-boost converter, tested under conditions of 20 V input and -15 V/1.5 A output.

If it is required to use the EN pin to configure the UVLO (Under-Voltage Lockout) of the inverting Buck Boost converter, a resistor divider can be set at the EN pin as shown in Figure 6.

The turn-on voltage V_START remains unchanged because there is typically no negative output voltage when the inverting Buck-Boost converter starts up.

After the inverting Buck-Boost converter starts up, the turn-off voltage V_STOP needs to account for the negative output voltage:

Taking the SGM61630 as an example, V_ENH = 1.17V, V_ENL = 1.12V. Set R_EN1 = 430kΩ, R_EN2 = 30kΩ, I1 = 1μA, I2 = 3.7μA, -V_OUT = -15 V. Then the turn-on voltage V_START is 17.51 V, and the turn-off voltage V_STOP is 0.15 V.

3.2 Synchronization Signal Interface Design

For Buck IC with a SYNC input pin, if the inverting Buck-Boost converter is required to synchronize with an external signal, a simple level shifter is needed, as shown in Figure 7.

When SYS_SYNC is high, Q1 turns on, V_IN provides the drive voltage V_GS to Q2 through the resistor divider (R1, R2), Q2 turns on, and V_IN pulls the SYNC pin high through the resistor divider (R_SYNC1, R_SYNC2). Note that the maximum rated voltage of the SYNC pin is typically low, so a Zener diode ZD1 is required to protect the chip from damage. Considering power dissipation, the resistance of the resistor divider from V_IN to System GND should not be too small. Therefore, in scenarios with high synchronization frequencies, a P-MOSFET with a small gate charge Q_G should be selected for Q2.

When SYS_SYNC is low, Q1 turns off, then Q2 turns off. After Q2 turns off, the SYNC pin is pulled down to -V_OUT through R_SYNC2. Due to the junction capacitance C_j of the Zener diode ZD1, there will be an additional delay t_delay between the valid synchronization signal and the rising edge of SW (this delay does not include the internal circuit delay of the chip).

Taking the SGM61630 as an example, set R1 = 499 Ω, R2 = 1 kΩ, R_SYNC1 = 1kΩ, R_SYNC2 = 200Ω in Figure 7. The synchronization mechanism of this Buck IC is that the rising edge of SW synchronizes with the falling edge of SYNC. The falling edge of SYS_SYNC turns off Q2. After Q2 turns off, C_j discharges through R_SYNC2. When the voltage at the SYNC pin discharges from the Zener voltage V_Z of ZD1 to the SYNC pin low threshold V_{SYNC_L}, the power switch turns on. This causes the rising edge of SW to lag behind the falling edge of SYS_SYNC. The delay time is:

From the above equation, it can be seen that for high-frequency synchronization requirements, a Zener diode with a smaller junction capacitance should be selected. The synchronization waveforms of the SGM61630 is shown in Figure 8.

3.3 PG Signal Interface Design

If the system does not require the Power Good (PG) flag signal from the inverting Buck-Boost converter, the PG pin can be left floating. If the system needs to obtain the PG signal to indicate to the MCU that the output voltage is within the specified range, the PG flag signal needs to be level-shifted to the system ground. The shifting circuit is shown in Figure 9.

When the output voltage is not fully established, the internal Q3 of the chip is turned on, and PG is pulled down to -V_OUT. At this time, Q1 is off and Q2 is on, and SYS_PG is pulled down to system ground. When the output voltage is fully established, Q3 turns off, and PG is pulled up to (-V_OUT+V_Z). At this time, Q1 turns on, and the gate-source voltage of Q2 becomes negative, turning it off, and SYS_PG is pulled up to the logic level V_LOGIC. Note that if the maximum rated voltage of the PG pin is relatively low and V_OUT is large, a Zener diode ZD1 should be added to protect the chip from damage.

Taking the SGM61630 as an example, set R1 = R2 = 100 kΩ, R3 = 10 kΩ in Figure 9. Figure 10 shows the waveforms of SYS_PG during Power-on and Power-off of the inverting Buck-Boost converter, tested under conditions of 24 V input and -15 V/0 A output.

4 Design Example

This chapter will design an inverting Buck-Boost converter based on the SGM61630 Demo Board (Buck)^[1].The design targets are shown in Table 2.

4.1 Schematic 

The schematic of the inverting Buck-Boost converter is shown in Figure 11.

To preliminarily verify the feasibility of this solution, the connection method can be directly modified on the SGM61630 Demo Board in Buck topology to reconfigure it into an inverting Buck-Boost topology, as shown in Figure 12. For actual new projects, it is necessary to re-layout the PCB according to the layout considerations for Buck-Boost converters to achieve optimal performance.

Notes:

1. Disconnect the lower-side connection of the original input capacitors C1, C1A, and C1B from IC GND, and reconnect them to the left pad of L1 (System GND). The reconnection wires should be as short as possible to minimize the impact of parasitic inductance on the input voltage.
2. Connect a 24 V power supply between "VIN" and "VOUT" on the Demo Board; connect an electronic load between "VOUT" and "GND" on the Demo Board.
3. Replace the inductor with a 22 μH inductor.

4.2 Key Parameter Calculation

The duty cycle of the inverting Buck-Boost converter is:

To facilitate the evaluation of the voltage withstand capability of the chip's VIN and SW pins, as well as the selection of related peripheral components, the voltage stress V_MAX of the Buck regulator is calculated as V_MAX = V_IN + V_OUT = 39V.

To balance inductor size and converter efficiency, select an inductor current ripple ratio of 0.35. The inductance value is then:

In this design example, L = 22 μH is selected. The inductor peak current is:

This is less than the minimum value of I_LIMT (3.5 A) specified in the SGM61630 datasheet^[2].

The inverting Buck-Boost converter has a right-half-plane zero (RHPZ), which increases gain and reduces phase at high frequencies, significantly and negatively impacting the control loop response and potentially causing system instability. The right-half-plane zero frequency for this design example under full load (worst case condition) is:

To ensure sufficient phase margin and system stability, it is generally recommended to set the system's crossover frequency to less than 1/4 of the RHPZ frequency. Therefore, it is necessary to reduce the inductance to increase the RHPZ frequency, or increase the output capacitance to reduce the system's crossover frequency. It is particularly important to note that in the inverting Buck-Boost converter architecture, the feedforward capacitor in the phase compensation network should be added with caution. Although the feedforward capacitor can improve phase margin, it simultaneously causes the gain curve in the magnitude-frequency characteristic to shift upward, which will cause the crossover frequency to move toward the RHPZ frequency, thereby introducing potential system stability risks.

To ensure that the system's crossover frequency is less than 1/4 of the RHPZ frequency, in this design example, two 47 μF / 25 V X5R capacitors in parallel are used for C_OUT.

4.3 Test Results

5 Conclusion

Reconfiguring a Buck converter into an inverting Buck-Boost converter requires the following steps:

1. Calculate the maximum voltage on the converter: V_IN + V_OUT.
2. Use Table 1 to calculate the maximum inductor current.
3. Select an appropriate Buck IC (meeting the voltage and current stress requirements).
4. Refer to the datasheet to determine component values such as the frequency-setting resistor and
   feedback divider resistors.
5. Evaluate whether additional designs such as auxiliary circuits or level-shifting circuits are required.
6. For preliminary verification, establish connections on the existing Buck Demo board according to Figure
   12:
   1. Redefine the positive output terminal of the Buck circuit as system ground;
   2. Use the IC GND node of the Buck circuit as the negative output terminal;
   3. Keep the input positive terminal unchanged.
7. Special attention should be paid during implementation:
   1. Optimize the layout of input/output capacitors;
   2. Ensure the quality of the feedback (FB) signal path;
   3. Keep the SW node traces as short as possible and away from sensitive signal paths.

6 References

[1] SG Micro Corp. SGM61630 Demo Board Test Report [EB/OL]. https://www.sg-micro.com/evm-detail/EVKIT-SGM61630.
[2] SG Micro Corp. SGM61630 Datasheet [EB/OL]. (2023-12). https://www.sg-micro.com/rect/assets/2e4aa3c1-fd17-4b20-ac75-892cfe5f2e56/SGM61630.pdf.

7 Appendix